[i2c] mixed-speed I2C system

[Nishanth Menon]

Jean,

Thanks for clarifying most of the views :).

Jean Delvare stated on 4/2/2007 4:53 AM:Jean Delvare stated on 3/30/2007
1:38 PM:
>> Thanks.  It makes more sens to be accurate per message.
>>     
>
> For HS-mode, yes, this is a device attribute. For fast-mode, no, as the
> whole bus is either in standard-mode or in fast-mode; this is not a
> device attribute.
>   
I agree. that makes sense with HS and FS devices on the same bus.
> Also note that it might be useful to be able to set the bus speed
> itself, independently of the different modes. For example, most SMBus
>   
> masters run at 16 kHz, but some SMBus masters can alternatively switch
> to 64 kHz. The software bit-banging implementation can also operate at
> different speeds ranging from 1 to 250 kHz. I believe that fast-mode
> support would be implemented that way, as standard-mode and fast-mode
> are really almost the same except for the max speed.
>   
Are you suggesting that the device registration also provide the device
speed and we program the i2c_clk speeds run-time (@ xfer_msg) as being
dependent on the device?
> properly, in particular I seem to remember that i2c-algo-bit doesn't. I
> don't think that multimaster busses are well tested under Linux in
> practice.
>
>   
Any plans of bringing i2c slave support? some controllers do have slave
or master support on the same bus.. is it crazy to imagine a USB OTG
kind of architecuture where we slip from master to slave and back....
just thinking wild...

Regards,
NM