[i2c] [PATCH] Add polling transfer for i2c-pxa

Mike Rapoport mike at compulab.co.il
Wed Nov 14 08:21:59 CET 2007


Jean Delvare wrote:
> Hi Mike,
> 
> On Tue, 13 Nov 2007 13:47:31 +0200, Mike Rapoport wrote:
>> eric miao wrote:
>>> 2. When switch to next segment message, a repeated restart would be better
>>> send to hold the I2C bus. That seems to be what the original interrupt driven
>>> code is doing...??
>> I was not sure it is necessary to repeat restart because polling transfer cannot
>> be interrupted.
> This is completely unrelated. Repeated starts is something that the
> slave chip expects as part of the I2C protocol. Doing a stop and a
> start instead of a repeated start means (depending on the chip) a
> different transaction. It doesn't have anything to do with the code
> being interruptible or not.
> 

Fixed (hopefully :) ).

-- 
Sincerely yours,
Mike.


Signed-off-by: Mike Rapoport <mike at compulab.co.il>

 drivers/i2c/busses/i2c-pxa.c |  178 ++++++++++++++++++++++++++++++++++++++++++
 drivers/i2c/i2c-core.c       |   20 +++++-
 include/linux/i2c.h          |    4 +
 3 files changed, 201 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 6426a61..ad6e97e 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -554,6 +554,183 @@ static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 	writel(icr, _ICR(i2c));
 }

+static int i2c_pxa_isr_set_cleared(struct pxa_i2c *i2c,
+				   unsigned long set_mask,
+				   unsigned long cleared_mask)
+{
+	int timeout = 10000;
+
+	while (((readl(_ISR(i2c)) & set_mask) != set_mask) ||
+	       ((readl(_ISR(i2c)) & cleared_mask) != 0)) {
+		udelay(10);
+		if (timeout-- < 0)
+			return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
+{
+	/* make timeout the same as for interrupt based functions */
+	long timeout = 2 * DEF_TIMEOUT;
+
+	/*
+	 * Wait for the bus to become free.
+	 */
+	while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
+		udelay(1000);
+		show_state(i2c);
+	}
+
+	if (timeout <= 0) {
+		show_state(i2c);
+		dev_err(&i2c->adap.dev,
+			"i2c_pxa: timeout waiting for bus free\n");
+		return I2C_RETRY;
+	}
+
+	/*
+	 * Set master mode.
+	 */
+	writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
+
+	return 0;
+}
+
+static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
+			       struct i2c_msg *msg, int num)
+{
+	int ret = 0;
+	u32 icr;
+
+	ret = i2c_pxa_pio_set_master(i2c);
+	if (ret)
+		goto out;
+
+	i2c->msg = msg;
+	i2c->msg_num = num;
+	i2c->msg_idx = 0;
+	i2c->msg_ptr = 0;
+	i2c->irqlogidx = 0;
+
+	i2c_pxa_start_message(i2c);
+
+	for (i2c->msg_idx = 0;
+	     i2c->msg_idx < num;
+	     i2c->msg_idx++, i2c->msg++) {
+		if (i2c->msg_idx > 0 && !(i2c->msg->flags & I2C_M_NOSTART)) {
+			icr = readl(_ICR(i2c)) &
+				~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
+			/*
+			 * Write the next address.
+			 */
+			writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
+
+			/*
+			 * And trigger a repeated start, and send the byte.
+			 */
+			icr |= ICR_START | ICR_TB;
+			writel(icr, _ICR(i2c));
+		}
+
+		ret = i2c_pxa_isr_set_cleared(i2c, ISR_ITE, 0);
+		if (ret)
+			goto out;
+
+		/* update the irq log same way is interrupt based transfers */
+		if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
+			i2c->isrlog[i2c->irqlogidx++] = readl(_ISR(i2c));
+
+		writel(ISR_ITE, _ISR(i2c));
+
+		for (i2c->msg_ptr = 0;
+		     i2c->msg_ptr < i2c->msg->len;
+		     i2c->msg_ptr++) {
+			icr = readl(_ICR(i2c)) &
+				~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
+			icr |= ICR_TB;
+
+			if (i2c->msg->flags & I2C_M_RD) {
+				if (i2c->msg_ptr == i2c->msg->len - 1)
+					icr |= ICR_STOP | ICR_ACKNAK;
+
+				i2c->icrlog[i2c->irqlogidx-1] = icr;
+				writel(icr, _ICR(i2c));
+
+				ret = i2c_pxa_isr_set_cleared(i2c, ISR_IRF, 0);
+				if (ret)
+					goto out;
+
+				writel(ISR_IRF, _ISR(i2c));
+
+				i2c->msg->buf[i2c->msg_ptr] = readl(_IDBR(i2c));
+			} else {
+				writel(i2c->msg->buf[i2c->msg_ptr], _IDBR(i2c));
+				/* If this is the last byte of the
+				   last message, send a STOP. */
+				if (i2c->msg_ptr == i2c->msg->len - 1 &&
+				    i2c->msg_idx == num - 1)
+					icr |= ICR_STOP;
+
+				i2c->icrlog[i2c->irqlogidx-1] = icr;
+				writel(icr, _ICR(i2c));
+
+				ret = i2c_pxa_isr_set_cleared(i2c, ISR_ITE, 0);
+				if (ret)
+					goto out;
+
+				writel(ISR_ITE, _ISR(i2c));
+			}
+		}
+	}
+
+	i2c_pxa_stop_message(i2c);
+
+	/*
+	 * We place the return code in i2c->msg_idx.
+	 */
+	ret = i2c->msg_idx;
+	i2c->msg_ptr = 0;
+	i2c->msg = NULL;
+	i2c->msg_num = 0;
+
+out:
+	if (ret < 0)
+		i2c_pxa_scream_blue_murder(i2c, "timeout");
+
+	return ret;
+}
+
+static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
+			    struct i2c_msg msgs[], int num)
+{
+	struct pxa_i2c *i2c = adap->algo_data;
+	int ret, i;
+
+	/* If the I2C controller is disabled we need to reset it
+	  (probably due to a suspend/resume destroying state). We do
+	  this here as we can then avoid worrying about resuming the
+	  controller before its users. */
+	if (!(readl(_ICR(i2c)) & ICR_IUE))
+		i2c_pxa_reset(i2c);
+
+	for (i = adap->retries; i >= 0; i--) {
+		ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
+		if (ret != I2C_RETRY)
+			goto out;
+
+		if (i2c_debug)
+			dev_dbg(&adap->dev, "Retrying transmission\n");
+		udelay(100);
+	}
+	i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
+	ret = -EREMOTEIO;
+ out:
+	i2c_pxa_set_slave(i2c, ret);
+	return ret;
+}
+
 /*
  * We are protected by the adapter bus mutex.
  */
@@ -837,6 +1014,7 @@ static u32 i2c_pxa_functionality(struct i2c_adapter *adap)

 static const struct i2c_algorithm i2c_pxa_algorithm = {
 	.master_xfer	= i2c_pxa_xfer,
+	.pio_xfer	= i2c_pxa_pio_xfer,
 	.functionality	= i2c_pxa_functionality,
 };

diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 1a4e8dc..37e3cd9 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -33,6 +33,7 @@
 #include <linux/platform_device.h>
 #include <linux/mutex.h>
 #include <linux/completion.h>
+#include <linux/delay.h>
 #include <asm/uaccess.h>

 #include "i2c-core.h"
@@ -870,7 +871,24 @@ int i2c_transfer(struct i2c_adapter * adap, struct i2c_msg *msgs, int num)
 {
 	int ret;

-	if (adap->algo->master_xfer) {
+	if (in_atomic() || irqs_disabled()) {
+		int retries = 1;
+		if (adap->algo->pio_xfer == NULL) {
+			pr_debug("%s: algo has no poll xfer", __FUNCTION__);
+			return -EINVAL;
+		}
+		ret = mutex_trylock(&adap->bus_lock);
+		if (ret) { /* We get bus_lock, no ongoing I2C activity */
+			ret = adap->algo->pio_xfer(adap, msgs, num);
+			mutex_unlock(&adap->bus_lock);
+			return ret;
+		} else {
+			/* I2C activity is ongoing. */
+			/* FIXME: may be we should take the lock and
+			   abandon ongoing transfer */
+			return -EBUSY;
+		}
+	} else if (adap->algo->master_xfer) {
 #ifdef DEBUG
 		for (ret = 0; ret < num; ret++) {
 			dev_dbg(&adap->dev, "master_xfer[%d] %c, addr=0x%02x, "
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 8033e6b..7e24466 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -290,6 +290,10 @@ struct i2c_algorithm {
 	                   unsigned short flags, char read_write,
 	                   u8 command, int size, union i2c_smbus_data * data);

+	/* PIO xfer can be used in no-interrupts context */
+	int (*pio_xfer)(struct i2c_adapter *adap, struct i2c_msg *msgs,
+			int num);
+
 	/* To determine what the adapter supports */
 	u32 (*functionality) (struct i2c_adapter *);
 };



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